Precedence trunk selection in a central processor controlled communication switching system

ABSTRACT

A TRANSLATOR AND ROUTE SELECTOR OF A CENTRAL PROCESSOR INCLUDES A COMMON MEMORY WITH A SET OF CORES FOR EACH TRUNK TO RECORD ITS STATUS AS IDLE OR BUSY AT ONE OF SEVERAL POSSIBLE LEVELS OF PRECEDENCE. THE ROUTE-SELECTOR INCLUDES A STATUS-CIRCUIT WITH A FLIP-FLOP FOR EACH POSSIBLE LEVEL OF PRECEDENCE. DURING A FIRST SCAN EACH FLIP-FLOP IS SET IF A TRUNK IS FOUND AT THE CORRESPONDING STATUS, AND IF AN IDLE TRUNK IS FOUND IT IS SELECTED. IF NONE IS SELECTED A PREEMPT CONTROL FLIP-FLOP IS SET, AND THE SCAN IS REPEATED TO SELECT A TRUNK AT THE LOWEST LEVEL RECORDED BY THE STATUS CIRCUIT.

3,487,173 12/1969 Duthie etal.

David K. K. Lee

Chicago, 11].;

Howard L. Wirsing, Wiesbaden, Germany 828,568

May 28, 1969 June 28, 1971 GTE Automatic Electric LaboratoriesIncorporated Northlnke, IlL

inventors App]. No. Filed Patented Assignee PRECEDENCE TRUNK SELECTIONIN A CENTRAL PROCESSOR CONTROLLED COMMUNICATION SWITCHING SYSTEM 20Claims, 3 Drawing Figs.

References Cited UNITED STATES PATENTS 3,483,524 12/1969 De Bucketal.179/18(ES) 3,389,227 6/1968 Catterallet a1. 179/18(D) FOREIGN PATENTS1,277,371 9/1968 Germany 179/18(D) Primary Examiner-William C. CooperAssistant Examiner-Thomas W. Brown Attorneys-Cyril A. Krenzer,l(.Mu1l.erheim and B. E. Franz ABSTRACT: A translator and route selectorof a central processor includes a common memory with a set of cores foreach trunk to record its status as idle or busy at one of severalpossible levels of precedence. The route-selector includes a statuscircuit with a flip-flop for each possible level of precedence. Duringafirst scan each flip-flop is set if a trunk is found at thecorresponding status, and if an idle trunk is found it is selected. Ifnone is selected a preempt control flip-flop is set, and the scan isrepeated to select a trunk at the lowest level recorded by the statuscircuit.

PATENTEU JUN28 I971 SHEET 1 BF 2 8w no E565 AT AT- ill.

INVENTORS DAVID K.K. LEE HOWARD L WIRSING mmw xhm ntnv xmtm w N 3x1 N3mm v N 7E1 MNGP n N 3mm ATTORNEY PATENTFUJUN28I97I 3 5 ,359

SHEET 2 OF 2 541 DAI DSTI DPI FFIIECEIDENCE TITTIUNTT SETLECTTON TN ACENTRAL FTTUCESSOFT CONTROLLED COMMUNTCATTON SWTTCTTIING SYSTEM CTIOSSREFERENCES TO RELATED APPLICATIONS Essential matter for this inventionis found in a copcnding U.S. Fat. application by D. ll. T(. Lee and D.N. Wong for Traffic Control in a Network of Switching Centers, Ser. No.795,285 filed Tan. 30, I969, now Pat. No. 3,560,663, issued Feb. 2, I97I, hereinafter referred to as said Traffic Control application; and alsoin an application by H. L. Wirsing for a Trunk Preference Circuit for aCommunication Switching System, Ser. No. 749,l31 filed July 3|, l96ll,now Pat. No. 3,532,830 hereinafter referred to as said Trunk Scannerapplication.

The above-mentioned applications relate to the Communication SwitchingSystem described in U.S. Pat. No. 3,328,534 by TR. J. Murphy et al.,hereinafter referred to as the System patent. The switching networkmarker for this system is described in U.S. Pat. No. 3,4l3,421 by A. S.Cochran et al. for Apparatus to Select and Tdentify One ofa PossiblePlurality of Terminals Calling for Service in a Communication SwitchingSystem, hereinafter referred to as the Tdentifier patent.

Three copending U.S. applications for a Digital Control and MemoryArrangement, Ser. No. 667,170 by H. L. Wirsing and W. C. Miller, filedSept. 12, I967, now Pat. No. 3,533,073; Ser. No. 690,356 by G. F.Minarcik filed Dec. l3, I967, now Pat. No. 3,533,080 and Ser. No.690,348 by D. It. TC. Lee, J. R. Vande Wege and W. R. Wedmore, filedDec. 13, I967, now Pat. No. 3,533,079 hereinafter referred to as theMemory Sharing patent applications, disclose an arrangement of thecommon control equipment into three subsystems sharing a common memory.

A copending U.S. application for a Communication System Trunk Circuit,by L. L. Smith et al., Ser. No. 670,032, filed Sept. 25, 1967, now U.S.Pat. No. 3,524,934 hereinafter referred to as said Precedence TrunkCircuit, discloses a trunk circuit equipped to respond to a preemptsignal from the marker to cause a distinctive signal to be sent to theparties engaged in a call, and then to drop the connection to permitestablishing the priority call.

The type of logic conventions, and a description of the building blockcircuits including the flip-flops, is described in US. Pat. No.3,293,368 by W. R. Wedmore for a Marker for a Communication SwitchingNetwork, and in particular a schematic drawing is shown in FIG. 5T,described in columns 23, 2.4, as and W; referred to hereinafter as saidBuilding Block Description. Note that the marker unit described in thatpatent is used in an earlier switching system.

BACKGROUND OF THE INVENTION I. Field ofthe lnvention This inventionrelates to automatic switching systems and particularly to providingmultilevel preference or precedence and multilevel preemption ofcommunication paths in such switching systems.

2. Description of the Prior Art Tn a prior system including preferenceand preemption, a regular or normal trunk appearance and a second orauxiliary trunk appearance are provided for each of the outgoing trunkcircuits. The system is further arranged so that the marker will huntover the regular trunk appearances first and if any is found idle a callwill be established to this trunk appearance. The trunk is then markedwith the preference ofthe call. However, if all of the trunks appearbusy when searched over the regular trunk appearance, the marker thenhunts over the auxiliary trunk appearances. If any auxiliary trunkappearance is found in which a corresponding trunk is not engaged in thetransmission of a preference call, it will be preempted, i.e., scizedand the connection previously established over such trunk ortransmission circuit interrupted and the new call having a higherprecedence or preference level established over this facility.

If one attempts to extend such an arrangement and provide an additionaltrunk appearance for each level of preference or precedence, the amountof switching equipment must be greatly expanded because a small numberof trunks require a large capacity.

It is desirable to incorporate multilevel preference and preemption inan electronic switching system of the type hav ing a central processoroperating with a common memory, in which the status of each trunkcircuit is stored in the memory, and the route selector in the centralprocessor searches through the memory to find an available trunk. Ifeach trunk circuit is provided with an additional appearance for eachlevel of precedence, then a separate set of memory elements would berequired for each appearance, which further increases the cost of thesystem.

SUMMARY OF THE TNVENTTON it is an object of out invention to provide alarge plurality of preference levels and levels of preemption fortransmission paths in a switching system from a single appearance ofsuch a trunk or transmission path on the switching network.

According to the invention, a status circuit is provided which may becontrolled by storage equipment individual to each of the trunks of theselected group oftrunks, with the arrangement for selecting anindividual one of the trunks being arranged for joint control by thestatus circuit and the storage equipment. More specifically, theprecedence level indicated by the status circuit is the lowest level ofpreference of calls in progress over the trunks ofthe group.

In an embodiment of the invention incorporated in a switching systemhaving a central processor and a common memory, a set of memory elementsis provided for each trunk circuit in which the status of the circuit asidle or busy at some level of precedence is stored. The status circuitcomprises a set of flipflops, one for each level of preference, each ofwhich is set if any trunk is found in use at the correspondingprecedence level, during a first search in which an idle trunk isselected if it is found available. if no idle trunk is found, apreemption process is initiated to make another search to select anavailable trunk at the lowest level of precedence.

BTRTEF DESCRTPTION OF THE DRAWING FIGS. TA and TB, with FIG. TA placedabove FlG. TB comprise a functional block diagram ofthe route selectioncontrol circuits ofthe system disclosed in said system patent; and

FlG. 2A is a functional block diagram of the preemption portion of thetransfer buffer ofthe system.

In addition the following description makes reference to the FTGS. T-T3of said Traffic Control application, using the reference characters andfigure numbers thereof without specific reference to the application.

The description also refers to FIG. Tl of said Trunk Scannerapplication, which is referred to FTG. TSTT, and the referencecharacters of that FlG. are prefixed by TS.

DESCRTPTTON OF THE PREFERRED EMBODIMENT FIG. 9 of said Traffic Controlapplication is a block diagram of the translator and route selector ofthe switching system in which the invention is embodied. FTGS. TA and TBherein comprise a functional block diagram of the route selectioncontrol circuit 9T T. FlG. TA shows status and trunk selection circuits,while FIG. TB shows control flip-flops and associated logic circuits forroute selection control.

The principal portion of the status circuit comprises five flip-flopsMTLT, MIPL2, MFLI, MF'LA and MFL9, which operate in conjunction with theassociated logic circuits and five comparator type parity circuitsTP-SP. A flip-flop TSC is for trunk selection control to enable the liveAND gates ell- 4l5P. The outputs ofthe parity circuits TIPE5P are alsocon nected respectively to the inputs of the gates dllF- ldl to indicateavailable trunks, and the gates are interconnected so that only one ofthem may have a true output signal at a time, to thereby designate thetrunk selected on one of the five leads SPA-SP5.

Referring to FIG 1B, the flip-flop SLN (select line next) is set if theresults of the translation of the dialed digits indicates that aspecific line is to be selected, while the flip-flop STN (select trunknext) is set if a search is to be made of one or more groups of trunksto select one available for the call. When an available line or trunk isfound the flip-flop TES (terminating equipment selected) is set. if anavailable trunk is not found on the first search, the flip-flop PIP(preempt in process) is set to initiate a preemption search. If for anyreason there is no trunk available for preemption the flip-flop UPT(unable to preempt) is set. During the search operation one of the twoflip-flops RTG (reenter this trunk group) or TNG (try next group) may beset to control the order in which the trunks are searched.

The flip-flops of the group selection control circuit 911, as well as anumber of other signal conductors having their source therein, arelisted in Table l for reference, A number of flip-flops and other signalconductors having their source in other circuits of the translator androute selector 120 or the transfer buffer 121, which are connected asinputs to the logic gates herein, are listed in Table II, with theirsource indicated with reference to FIGS. 8 and 9, or HO. 3.

scan.

10 R Inhibit counter reset.

MPLl, 2, 3, 4, 9... Precedence value was found.

NES Not equipment selection translation.

. Preempt in process flip-flop.

. Signal to set preempt. used to reset route selection counters.

. Binary-coded decimal value of DPLl, 2, 3, 4; MPLQ,

Reset PIP.

Reenter this trunk group.

Scanning a group for trunk selection.

Selected trunk is from identified one of positions AE of a DPI9 word.

Trunk selection control flip-flop.

Terminating equipment selected indicating flip-flop.

Unable to preempt.

TABLE 11 Signals Source Description BOX-B15X... 500 TimingCPB in TXintervals -15. CNl-ll 905 (FIG. Coincidence found type. CPB 500 Clockpulse. 4 DAl-DJ15. 620 (Decoded). Decoded memory output digits. DDP1-10811 Decoded dialed priority digits. DPI1-25 Decoded processinstructions. DRI1-5 817 Decoded route digit indicator. DRNC13 817..Decoded route number. DRSCl-fi. 817. Decoded route sequence. DTIl-Bl.803. Decoded translation instructions. GLP 121.. General line preemptcommand.

. General reset pulse.

. Set preempt in process.

121 Command to set trunk 10 flip-flops (816) upon terminating equipmentselection. TAl-TJ4. 620 Memory output bits from translator read bufier620.

UPL 121 Unable to preempt line.

While the signals listed in Table II are described in said TrafficControl and Trunk Scanner application, a brief review of some of themmay be in order. The memory is word organized with 40 information bitsper word organized as 10 positions AJ, each of which comprises bitsdesignated 1-4. For the translator and route selector the words are readone at a time in successive operation cycles into the translator readbuffer 620, the outputs of which are designated TA1TJ4. For example,position A comprises bits TA1. TAZ. TA3 and TA4. which may beabbreviated TAl,2,3,4 or TA1-4. The four bits of each position may bedecoded as 16 signals, with decoded position A, for example, being oneof the 16 possible signals DAODA15.

The clock pulse and timing signals are best explained in said MemorySharing applications. Briefly the basic clock pulses comprise trains ofpulses on two conductors designated CPA and CPB. with each traincomprising l-microsecond pulses recurring at 10 microsecond intervals,with each pulse of each train occurring 5 microseconds after a pulse ofthe other train. And the operation cycle counter designated the TXgenerator is a l6-stage counter which is stepped once by each pulse fromthe train CPA to provide in succession the 10 microsecond intervalsignals TXOTX15. For the translator and route selector a word is readfrom memory once per operation cycle and appears in the translator readbuffer in the interval TXll, remaining there until cleared in theinterval TX7 of the next cycle, the word being rewritten into memory inthe interval TX6. Thus, processing for each word may begin in theinterval TX12.

For associative searches of the memory the coincident gating controlcircuits 905, shown in FIG. 10, are used to compare given digits storedin the transfer buffer with the digits in certain positions ofsuccessive words of the memory, with one of the coincidence signalsCN1CN11 being generated according to the type of word being searched.

Each word of the translator and route selector portion of the memory hasa processing digit stored in the 5 bits l4.l4, which is decoded by thedecode process instruction circuits 908 as one of the signalsDPIl-DPl25.

The dialed digits for a call may include a priority digit DP and arouting digit DR which are stored in the buffer circuits 811, andaddressing digits of which D1D7 are stored in buffers 812, 813 and 814.The priority digits may be decoded as DDP10 for flash override, DDPl forflash, DDP2 for immediate, DDP3 for priority, and DDP4 for routine."

The translation section of the memory contains a plurality of wordsgiving the translation information for particular codes. Thisinformation includes route selection information which is read from theappropriate word and stored in the buffer 817. It includes a route digitindicator having values DRDll-DRDIS indicating respectively whether aroute sequence, a route number, a trunk group number, an individual linenumber, or a group number plus a trunk tens number to designate up to 10lines for a PABX line search. The route sequence number designates oneor two words in memory containing up to six route numbers, a routenumber designates a word of memory containing up to three trunk groupnumbers, and a trunk group number designates a section of memorycontaining the status of all of the trunks of a group.

In the route sequence and route number sections of the memory an unusedroute number or trunk group position has a value 1515 stored for thetens and units digits, so that reading such a value indicates that theend of th sequence or the end of the route number has been reach e f'rhiis'in dicated in the route selection information buffer 817 bygenerating a signal SPIPC, which is supplied to the route selectioncontrol circuit 911. The storage equipment individual to each of thetrunks of the several groups of trunks is found in section 7 of thememory (FIG. 7), the trunk and line status section. For each group oftrunks there is a trunk group word having a process instruction of DPI8,a plurality of status words having a process instruction of DPI10, andtwo address words having process instructions of DPIll and DPI18 forsupplying addresses to the address generator to control proceeding tothe next operation in the sequence. The DPI8 group identification wordshave the group tens and units numbers in positions A and B, and a groupstatus digit in position D.

The DPI9 trunk status words each store the status of five trunks of agroup. Positions AE store busy-idle indicators for the five trunksrespectively, bits Fl-HZ store preseize and originating busy bits forthe five trunks, bit H3 has a value of one for the first word having thefirst five trunks for a given trunk tens number. and a zero for thesecond work having the last five trunks thereof. bits lid-l4 store thetrunk tens number, and bits H l-M are the process instruction DPI9.

The busy idle indicator in each of the positions A--E has decoded valuesdesignated DBI1DBI15 with the values indicating the status as follows:l-flash. Z'immediate, 3-priority. troutine, 9-queueing idle, lO-flashoverride, ll-equipment not in service, l3-true idle, l4-maintenancebusy, and l5-not equipped.

In FIG. 1A. the OR gates 11P16P each receive the decoded outputs of thebusy-idle indicator for all five trunks of a word for one value thereof.The outputs of these gates are supplied respectively to AND-gates21P-26P, which are enabled by a signal SCGN during a trunk search. Thesignal SCGN is supplied in response to coincidence of the signals STNand DPW via gates 18F and 191. Gate 17? supplies a true signal during aPABX-type search as indicated by the signal DRDI5 when in the designatedword as indicated by the signal C116 which in coincidence with thesignal DlPl9 at gate 19? also can generate the signal SCGN.

The MPL flip-flops record the various levels of priority found in thebusy-idle indicators during a trunlt search. Thus, while reading one ofthe status words with the signal SCGN being true, if any one of the fivetrunks is busy at flash" precedence as indicated by one or more of thesignals DAl- -DE1 being true the output of gate 11? via 21F supplies aDC set signal to the input of flip-flop MPLI, if one of them is busy atimmediate precedence level the signal B12 from the output of gate 121 issupplied via gate 22? to a DC input of flip-flop MPLZ, ifany of them isbusy at priority precedence level the signal B13 from the output of gate13? via gate 23? supplies a DC signal to flip-flop MPL3, if any of themis routine busy the signal B14 from gate 14F via gate 24? supplies theDC signal to flip-flop MPIA, and if any of them is queueing idle" theoutput of gate 151 via gate ZSP supplies a DC signal B19 to the input ofgate MPL9. If any of the five trunks is true idle" the output of gate16? via gate 215? supplies the signal Bllfl.

The flip-flops MPLll-MPL9 which have received a DC input are set inresponse to the pulse signal B13X (clock pulse 13 during interval TX13.Once any one of these flip-flops has been set it remains set during thesearch of the remaining words of the group, and during each wordadditional flip-flops may be set in accordance with the status found.They will also remain set during the search of successive groups in asearch involving alternate routes. Thus at the end of the search of allof the trunk groups available for a routing, the MPL flip-flops indicateeach status level which has been found throughout the search.

If a trunlt is found with a true idle" status B113 it is immediateiyselected. However, if no true idle trunk is found in the complete searchit is desirable to determine what was the lowest level of precedencethat was found. The AND-gates 31P-3dl decode the outputs of the MIPI.flip-flops to determine this level. The lowest level which may beindicated is queueing idle" with flip-flop MPH) set to supply a signalon lead MPLQ. The next lowest level is routine" with flip-flop MPLd set,which via gate 34? supplies a signal DPLl, in response to the signal onlead MPL l being true and that on MPL9 being false. The next lowestlevel is priority indicated by flip-flop MIPL3 being set and none of thelower priorities being true, which via gate 33? supplies a signal DPL3.The next lowest level is irnmediate" which is indicated by flipflop MPLZbeing set and none of the lower priorities being true, which via gate32? supplies a signal DPLZ. The next lowest level is flash" as indicatedby flip-flop MPLll being true and none ofthe lower priorities beingtrue, which via gate 31? supplies a signal DPLll. The signal on one ofthe leads DPL1- DPLi, MPL9 or B113 is encoded into binary coded decimalform by the ORgates 35P-38P onto the leads PRLl, PRL2, PRLd and PRLh.These four leads are connected as one set of inputs to each of thecomparison parity circuits llP-SP. The other set of inputs to the paritycircuits are the busy-indicator values for the five trunks of a wordrespectively from the translator read buffer 620. For example paritygate 1? has one set of inputs with signals TA1,2,3,4 from position A,which is the binary-coded-decimal value of the busy-idle indicator forthe first trunk in the word; and a second set of inputs comprising thesignals PRLl 3,4,8 indicating the lowest level of priority found in asearch. If these inputs are equal bit for bit the output of the paritycircuit is true, which indicates the corresponding trunk is availablefor this call.

If one or more of the trunk circuits from a word is available theAND-gates l1IP45P select one of them, if the flip-flop TSC has been set.If any one of the signals TF1, T1 3, T61, T63 or Tl-Il is true thisindicates that the corresponding trunlt has been preseized for aterminating call, and therefore these leads are connected to therespective ones of gates 411 -4151 as inhibit inputs. The outputs ofeach of these gates is con nected as an inhibit input to each of thesucceeding ones so that if any one of the signals becomes true itinhibits all of the succeeding ones to thereby select only one trunlt.

If during any search a true idle trunk is found as indicated by thesignal BI13, that trunk is selected during the same operation cycle.This is accomplished by enabling the gates 35P-3fP to provide abinary-coded-decimal value of 13, signals PRLl, PRL l and PRL8 beingtrue. Then all of the parity circuits lP-5P for the trunks in a wordwhich are true idle will become true. The signal B113 via OR'gate MPalso enables gate 50?, since the signals T135 and TNG are false at thistime and the signal SCGN is true. The output of gate 50? in coincidencewith the pulse BX sets the flip-flop TSC. Then if the true idle trunk ortrunks has not already been preseized for another call, there will be asignal on one of the leads SPASPE.

A trunk may also be selected during a second search if the signal PIP istrue for preempt in process, or a queueing idle trunk has been found asindicated by the signal on lead MPL9 and the flip-flop RTG has been setto enable gate 46?, either of these signal conditions being used toenable gate 50F to set the flip-flop TSC. If during a second search theflip-flop PIP has been set to enable gate 49]? it may be reset by thesignal RPIP if one of the four inputs of OR-gate 431? is true. The firstthree inputs indicate that a queueing idle" or true idle" trunk isavailable, and the fourth input is the output of the unable to preemptflip-flop UPT.

At the beginning of a sequence of operations in the translator and routeselector a signal BRS from gate 53F is generated as a beginning reset ofcertain flip-flops. The first word of each section has a processingdigit DPIltS and the identity of the section in position A, so thatcoincidence of the signals DA1 and DPIll6 at gate 53? indicate the firstword of the first section.

When starting a scan of a trunk group in the status section the groupword is addressed, the coincidence of the signals DP18 and the output ofthe comparison parity circuit TCG1- 2 in FIG. 10 along with the output.of flip-flop TAC enables gate 1013 to supply the coincidence signal CNS.If this is a line selection the routing-digit-indicator signal DRDM istrue to enable gate 52F; and if the signals DRDIl and DRDIS are bothfalse the gate 62? is enabled to supply a signal to flip-flop STN, theenabled one of these flip-flops being set in response to the pulse BMX.

The gates 54P61P are used for preemption control during a line selectionin accordance with the decoded value of the dialled priority digit andthe value of the busy-idle indicator from gates IlP-14P. The signal GLPis the general-line preemption signal from the translator write circuits121, and this signal in coincidence with the output of gate 61P via gate64P supplies a DC input signal to the upper input of flip-flop PIP.

Preemption during trunk selection is controlled via gate 76P which isinhibited by a signal on either of the leads PIP or RTG being true, butis otherwise enabled in response to an output from OR-gate 75?. Theoutput of gate 76? is supplied as a DC input to the second input offlip-flop PIP and also as a signal PIPE to the transfer butter to resetthe route sequence and route number counters to permit a new search ofall of the trunk groups for the routing.

The first input of gate 75P is from AND-gate 7lP which has inputs onlead DRDI2 indicating a route number type search, CN] 1 which via gate1046 of FIG. indicates coincidence of the route number in the routenumber section, and SPIPC which indicates a value of for the route tensnumber to designate that this position is not used and therefore allroute numbers have been searched. Gate 72? has an input CN9 whichindicates coincidence in reading a word in the route sequence section,and the signal SPIPC which indicates a value of 15 for the route numbersignifying that all route numbers have been searched.

Gate 73P has inputs DPLIO which indicates that the end of a trunk grouphas been reached in the status section, TES inhibit to indicate thatterminating equipment has not been selected, TB3, inhibit, and theoutput of gate 70P. The signal TB3 is true if this is the end of asubtrunk group. There are four inputs to gate 70F from gates 65P-68Prespectively. Gate 65F has inputs DRDIZ indicating a route number typeselection, and DRNC3 indicating that the route number counter hasadvanced to it maximum value. Gate 66P has inputs DRSC6 indicating thatthe sequence counter has advanced to its maximum value and DRNC3indicating that the route number counter has advanced to its maximumvalue. Gate 67P has inputs STN for select-trunk-next type operation, andDTI8 which is a translation instruction for maintenance busy andretranslation loop around. Gate 68P has an inhibit on lead NES for atranslation instruction which is not for equipment selection, and aninput from gate 69F which is true in response to signal DRDI3 or DRDISindicating a trunk group or PABX group type selection respectively.

The last input of gate 75? is from gate 74P, which has inputs DRDIlindicating a route sequence type selection, DRSC6 indicating that theroute sequence counter has advanced to the last value, CNll from gate1046 which indicates a route number coincidence in the route numbersection during either a DRDll or DRDI2 type of search, and SPIPC whichindicates a value of 15 as a trunk group tens number in the route numbersection to designate that all trunk groups have been searched. Theoutput of gate 74P is designated ICR for inhibit counter reset and issupplied to the transfer buffer circuits.

The flip-flop TES is set in response to the signal STKT from thetranslator write circuits 121, which becomes true whenever a line ortrunk is selected.

The flip-flop UPT for unable to preempt is set in response to a signalfrom gate 87?, or a signal on lead UPL, in coincidence with the pulsesignal on lead BSX. The signal UPL is from the translator write circuits121 indicating an unable to preempt the line. Gate 87P has one inputfrom a lead PIP indicating that the preempt in process flip-flop hasalready been set, and another input on lead MPL9 as an inhibit toprevent the setting of the unable to preempt flip-flop if a queueingidle trunk has become available. The last input of gate 87? is fromOR-gate 86P whose principal input is from gate 85!. The signal PE isfrom the preempt flip-flop of the transfer buffer, FIG. 2A. The otherinput of gate 85? is from OR-gate 75? which is the preempt signal. Thusif a preempt search has been completed without finding an availabletrunk, and there is a repeated attempt to set the flip-flop PIP, thesignal instead via gates P, 86F and 87P sets the unable to preemptflip-flop UPT. The second input of gate 86? is from gate 67F via leadSUPTE. The third input of gate 86F is from gate 84? having an inhibitinput on lead SLN to indicate this is not a line selection, and anotherinput from gate 83?. The various inputs to gate 83? from gates 77P-82Pcompare the dialled priority digit to the precedence found from the gate31P34P and also from the flip-flops MPL1-MPL9 to indicate one of thefollowing conditions: precedence I call and lowest precedence on scanwas 1, precedence 2 call and lowest precedence on scan was 2, precedence3 call and lowest precedence on scan was I, 2 or 3, lowest precedence onscan was 10, or a precedence 4 call.

The flip-flop RTG (reenter trunk group) is set when the end of a trunkgroup is reached as indicated by the DPI10 process instruction, if it isnot the end of a subgroup by the inhibit on lead TB3, the terminatingequipment had not been selected as indicated by an inhibit on lead TES,the flip-flop RTG has not already been set as indicated by an inhibit onlead RTG, and a queueing idle trunk has been found as indicated by thesignal on lead MPL9. The flip-flop is reset in response to a signal onTBS when the terminating equipment is selected.

The flip-flop TNG (try next trunk group) is set in response to thesignal from gate 94?. The first input is an inhibit on lead NES if thisis not an equipment selection type translation. The second input is fromgate 73P for the types of preemption control designated by that gate,and the third input is from gate 94P. The first input of gate 93P isfrom gate 90P having one input on lead CNS indicating coincidence on aDP18 group word in the status section, and an input from OR-gate 98Pwhich has several inputs depending on the decoded value of the statusdigit as follows: DD2-group busy to all traffic, DD4- group busy to alloutgoing traffic, DDS-group not preemptable, DD7-group available forpriority traffic only on a terminating selection, or DD8-group availablefor routine traffic only on a terminating selection. The decoded dialleddigit DDP4 (routine precedence) is supplied as an input to gate 9GP fora routine preference call, and as an inhibit input to gate 97P to enablethat gate when this is not a routine preference call.

The last input of gate 93F is from gate 92P which has a first input fromOR-gate 95? indicating that this is a route sequence or route numbertype selection so that there are a plurality of trunk groups to besearched, an input DPI10 indicating the end of a trunk group in thestatus section, and inhibit inputs on leads TES to indicate theterminating equipment has not been selected, RTG to indicate that it isnot a reenter trunk-group type operation, and TB3 indicating it is notthe end of a subtrunk group.

The flip-flop TNG is reset each time the DP18 word at the beginning of atrunk group is read, during interval B12X near the beginning of theoperation cycle for translations.

TYPICAL OPERATION A call is described in said Traffic Controlapplication under the heading General Operation of the System for aTypical Call starting on page 7, and the heading Detailed Operation forCode Operation starting on page 38. For an understanding of therecording of the status of the lines and trunks in the status section ofthe memory, said Trunk Scanner application, and in particular Section Ddescribing the translator write circuit 121, is also relevant, Theoperation is described in Section D2. Translator Write Operation"starting on page 37 thereof.

In addition to the assumptions made by the call description in saidTraffic Control application, assume that the calling digits receivedfrom the originating party include a priority digit having a decodedvalue DDP2 which designates a precedence level of immediate." Note insaid Trunk Scanner application description of the operation of thetranslator write circuits, under the subheading Precedence Up-GradeTranslation" that the priority digit is written into the status sectionofmemory for the originating line or trunk.

in said Traffic Control application, at the beginning of the descriptionof the detailed operation for code translation, the information loadedinto the transfer buffer during the load cycle is described. In additionthe priority digit is stored in block fill. The description may befollowed in said Traffic Control application up to page 42 where thetranslator address is set to the DPIfl trunk group word. At this timethe signal CNS from gate I013 is true. This signal is applied at gate MPin FIG. IE. it has been assumed that the routing digit indicator has avalue DRDlZ, and the signal on lead NES is false. The output of gate 62Pin coincidence with the pulse on lead BMX sets the flip-flop STN tocontrol the select trunk next" operation. The address advances by one tothe first DPI9 word. The route selection control circuits 9H check thebusy-idle status of the five trunlts in each DPI9 word. Assume that inthe first trunlt group scanned that all trunks are busy at one of thethree highest levels of priority. For example if in the first word for aset of five trunks the first and third are busy at the immediateprecedence level, the signals lDAZ and DCZ are true, which via gates IZPand MP sets flip-flop MPLZ. If the second and fifth trunlts are busy atthe flash" precedence level, the signals DBI and DEl via gates HP andZIP set the flip-flop MPLl. If the fourth trunk is busy at the flashoverride" precedence the signal DDIO will appear; which is not used inFIG. IA, since this level is not preemptable. The succeeding words ofthe trunlt group are similarly scanned, and when the DPlll word isreached at the end of the group the only ones of the MP1. flip-flopswhich are set will be MPLl and MPL2.

The translator again advances to the address of the DPllll word. Thesection four start word address from bits F2--I3 is entered in theaddress flip-flops of apparatus 902, and the flipflop ETA is set toreturn to section il for the number of the next trunk group. Theflip-flop ATA is set to advance through the route number section toagain find coincidence with the route number of DPI word. Since theroute number counter has been advanced one step, the trunk group B frompositions E and F is now selected and its identity transferred into theTG flip-flops of block are. The route selection process now proceeds tosection 6 as before to find the work having this new trunk group, andthen transfers to the corresponding group address in section 7. In thefirst DPI9 word of the group, assume that the five trunks are busy atthe routine" precedence level, so that the signals DAd-DEd via gates MPand IMP set the llip'flop MPL l. Assume further that the remainingtrunks of the group are busy at r0utine, immediate, or flash" precedencelevels, so that at the end of the scan of the entire trunk group whenthe DPIl0 word is reached'the flip-flops MPLI, MPLZ, and MPL l are inthe set condition, while flip-flops MPL3 and MPL9 remain reset.

The section 4 start word address will again be obtained from the DPllllword, and the route number section is entered to again find coincidencewith the route number on a DPll5 word. The route number counter is nowadvanced to read the trunk group C from positions G and H which is trunkgroup 31. This trunk group will then be scanned in the status section,and it is assumed that there are no idle trunks, and that at the end ofthe scan the flip-flops MPL3 and MPL9 are still in the reset condition.Upon reaching the DPlll0 word at the end of the group, the route numbercounter will have been advanced so that the signal DRNCS is true. Thissignal in coincidence with the signal on lead DRDllZ enables gate 65F,and its output is applied via gate '70P to the input of gate 73?. Sincethis is not the end of a subtrunk group the signal on lead TB3 is falseand the terminating equipment has not been selected so that the signalon lead TES is false. Therefore the signal on lead DPIltl enables gate731, with the output supplied via gates 73P and '76? to set theflip-flop PIP upon the occurrence of the pulse on lead BISX. The signalon lead PIPE from gate 7I6P is supplied to block ill? of the transferbuffer to reset the route number counter.

The operation for scanning the trunk groups of this route number is nowrepeated to search for a trunk which may be preempted. It has beenassumed that the flip-flops MPLll, MPLZ, and MPIA are now set, withflip-flops MPL3 and MPL9 remaining reset, so that the signal on lead DPLl from gate 34F is true. Therefore from gates 35P-30P, the signal onlead PRIA is true while the signals on leads PRLI, PRU. and PRL8 arefalse. These four signals are supplied to all of the five comparatorparity circuits 1P5P. When the flip-flop PIP became set the signal viagate MP in coincidence with the signal SCGN enabled gate 50P to set theflip-flop TSC. As each word of the trunk group is scanned, the binarycoded signals on the leads TAl,2,2,t-TE1,2,3,4I are supplied to theparity circuits llP-5P to compare the priority level status storedtherein to the priority level 4, which is the lowest priority of all ofthe trunks which may be used for this call. During the scan of the firsttrunk group, all of the trunks are still busy at one of the top threepriority levels, so that the scan proceeds to the second trunk group asbefore.

In the first DPI9 word of the second group, which is trunlt group 32,the route selection control circuit 911 finds that the trunk having theequipment number 3200 is busy at the routine" priority level. This isthe first trunk, whose status is stored in the first word for thisgroup. Therefore at the parity circuit 1? the signal TAB in coincidencewith PRLd true and T1, TA2, TA4 false in coincidence with PRLl, PRLZ,PRLb false enables the gate to supply the signal from its output to gate411?. The signal TFll for this trunk group is false, and the signal fromflip-flop TSC is true so that gate MP is enabled to generate the signalSPA. This signal is supplied to the status section write controlcircuits ll2ll shown in FIG. TS9. Since the signal TH3 is true for thefirst word, gate TS935A has a true output. The signal on lead TES isstill false at this time, so that the signal from gate TS935A via gateTS937A enables gate TS940A. This supplies a signal to lead WTF] to writethe preseize bit of this trunk, and via gate T594313 supplies an inputto gates TS951lA-959A. The priority digit from the transfer buffer blocktill is supplied in binary code which for the immediate" precedencelevel comprises the signals on DPI, DPl and DPO being false and thesignal on DP2 being true. The output from gate TSMIA via gate T5908makes the signal STKT true, and this signal via gate T8905 supplies aninput to the gates TS9l3-TS920, to thereby gate the priority digit tothe OR-gates TS92ll-TS92l and thence to the gates TS95llA-TS958A, andalso to corresponding gates for the other trunks. The immediateprecedence level is encoded as a signal on leads lTAl, WTAZ, ITA3, andlTA l. This value now becomes written into the memory.

In FIG. llB the signal on lead STKT in coincidence with the pulse onlead B7X sets flip-flop TES. The flip-flop TSC in PIG. 1A is reset ineach operation cycle by the pulse on lead BIX. The trunk tens number TKTfrom the memory, and the trunk units number TKU encoded on leads SUI-SUhfrom the encoding circuit TS912, are supplied to block 8% to completethe identification of the selected trunk.

On the scan of succeeding DPI9 words of the group the signal on lead TESinhibits gate 501 so that flip-flop TSC cannot be set. The translatoraddress continues to advance to the DPIIO word. This word contains thesending instr'uctions which are transferred into block 80.5, and mayalso contain prefix digits Pll-3 which if present are transferred intoblock 015. Also in FIG. 2A the preempt flip-flop PE was set in responseto the setting of flip-flop PIP, and remains set.

The flip-flop CP is now set to terminate the translation and routeselection process. The flip-flop DP is set, which causes the informationfrom the transfer buffer to be dumped into the register junctor memory.This includes the preempt bit from flip-flop PE which is dumped into bitBI of row 6, the terminating trunk identity being dumped into positions6-] of the same row.

The register sender via the date bus DB supplies the call information tothe marker. This information includes a bit set in response to thepreempt information from BI of row 6. This information is used by themarker to preempt the trunk as described in said Precedence TrunkCircuit application.

We claim:

I. In a communication switching system in combination, switchingapparatus, a group of communication paths connected to said switchingapparatus, storage means individual to each of said paths to store thepreference level of calls in progress over said paths, control means toselect said group of paths, and means to select an individual one ofsaid paths wherein a status circuit is provided and cooperates with saidstorage means to indicate a predetermined level of preference of callsin progress over the paths of said group, said means to select anindividual one of said paths including control connections with saidstatus circuit and with said storage means for joint control thereby;characterized in that said storage means comprises a common memoryhaving a plurality of storage elements, with a set of storage elementsindividual to each of said paths to store the preference levels of callsin progress over the path;

wherein said control means to select a group of paths, said means toselect an individual one of said paths, and said status circuit are partof a central processor interconnected to operate with said memory; withthe interconnections including a read buffer connected to receiveinformation signals from the sets of storage elements; wherein saidstatus circuit comprises a plurality of bistable devices and associatedlogic circuits, there being one of the bistable devices for each levelof preference which may be preempted, the bistable devices each havinginput circuit means coupled via some of the logic circuits to the readbuffer to set each bistable device in response to there being at leastone path of a group in use at the corresponding preference level asstored in the memory;

and further including means to receive and store a priority digitdesignating an authorized level of preference for a call.

2. A communication system in accordance with claim 1 characterized inthat said predetermined level of preference of calls indicated by saidstatus circuit is the lowest level of preference of calls in progressover the paths of said group of paths.

3. A communication system in accordance with claim 1 characterized inthat said means to select an individual one of said paths includesinterconnections jointly controlled by said status circuit and by saidstorage means to mark for selection all the paths having calls inprogress thereover of said predetermined preference level.

4. A communication system in accordance with claim 3 characterized inthat said predetermined level of preference of calls indicated by saidstatus circuit and marked for selection is the lowest level ofpreference of calls in progress over said group of paths.

5. A communication system in accordance with claim 1 characterized inthat said means to select an individual one of said paths includesinterconnections jointly controlled by said status circuit and by saidstorage means to mark for selection all of the paths having calls inprogress thereover having a lower preference level than saidpredetermined preference level.

6. In a communication switching system, the combination as claimed inclaim 1, wherein said means to select an individual one of said pathsincludes comparison means having one set of inputs coupled to theoutputs of said status circuit bistable devices via some of said logiccircuits, and another set of inputs coupled to said read buffer, tocompare the status of each path with the lowest level of preferencerecorded in said status circuit.

7. In a communication switching system, the combination as claimed inclaim 6, wherein the storage elements of said memory are organized intowords, with each word comprising the status storage elements for aplurality of paths, the information from one word of the memory at atime being transferred into the read butter;

wherein said comparison means comprises a number of comparison circuitsequal to the number of paths having their status recorded in each word,each comparison circuit being connected to compare the status of onepath of a word with the lowest level of preference recorded by saidstatus circuit;

and wherein for each said group of paths there are a plurality of wordsof the memory, means to scan so that the information from these words istransferred in succession into the read bufier, each bistable device ofthe status circuit being set each time a word of information istransferred into the read buffer if there is a path in use at thecorresponding preference level, so that upon the completion of a scan ofa complete group of paths each bistable device will be set if there isat least one path in use at the corresponding preference level in thegroup.

8. In a communication switching system, the combination as claimed inclaim 7, wherein said means to select an individual one of said pathsincludes an idle-detection circuit connected to said read buffer todetect the idle status for at least one path, said circuit beingconnected to the comparison circuits to indicate the presence of an idlecircuit, so that the idle path is then selected.

9. In a communication switching system, the combination as claimed inclaim 8 further including a preempt control bistable device which isconnected to be set upon the completion of a scan of all paths of agroup, and means to cause a repeated scan of the group to select a pathin use at the lowest level of preference recorded in said status circuitas determined by said comparison circuits.

10. In a communication switching system, the combination as claimed inclaim 9, further including an unable-to-preempt bistable deviceconnected to be set at the end of the second scan if no path isavailable at a lower level of preference than that permitted for thecall.

11. In a communication switching system, the combination as claimed inclaim 10, wherein there are provided a plurality of groups of paths foruse in a given routing to a destination, comprising a group for primaryrouting and at least one group for alternate routing, the selectioncircuits being arranged to scan all of the groups in succession on thefirst scan to search for an idle path and to set the bistable devices ofthe status circuit, and to set said preempt control bistable device atthe end of the complete first scan, to thereby cause initiation of asecond scan to search all of the groups to find a path available at thelowest level of preference recorded by the status circuit.

12. In a communication switching system, the combination as claimed inclaim 11, further including means to select a specific individual path,means responsive to that path being at a busy status as recorded in theset of memory elements therefor to set said preempt control bistabledevice, and means responsive to the setting of the preempt controlbistable device to preempt the line if its status is at a lower level ofpreference than the preference authorized for the call.

13. In a communication switching system, the combination as claimed inclaim 1, wherein there are provided a plurality of groups of paths foruse in a given routing to a destination, comprising a group for aprimary routing and at least one group for alternate routing, theselection circuits being arranged to select and scan all of the groupsin succession on a first scan to search for an idle path and to set thebistable devices of the status circuit.

14. In a communication switching system, the combination as claimed inclaim 13, further including a preempt control bistable device which isconnected to be set upon the completion of a scan of all of the paths ofall of the groups, to thereby cause initiation of a second scan tosearch all of the groups to find a path available at the lowest level ofpreference recorded by the status circuit.

15. In a communication switching system. the combination as claimed inclaim [4, further including an unable-topreempt bistable deviceconnected to be set at the end of the second scan if no path isavailable at a lower level of preference than that permitted for thecall.

16. in a communication switching system. the combination as claimed inclaim 1, wherein the status conditions which may be stored in the set ofstorage elements for a path include a true idle" and a queueing idle"status. paths having a true idle" status being selected in preference tothose having a queueing idle" status;

wherein one of the bistable devices of said status circuit is for"queueing idle," this being a lower level of preference than thatdesignated by any of the other bistable devices for busy at some levelof preference.

l7. ln a communication switching system, the combination as claimed inclaim l6, wherein there are provided a plurality of groups of paths foruse in a given routing to a destination,

the selection circuits being arranged to scan all of the groups insuccession on the first scan to search for a true idle" path and to setthe bistable devices of the status circuit,

selected to cause a repeated scan of that group to select a queueingidle path;

and alternatively means responsive to the queueing idle bistable deviceremaining in the reset condition and no idle path having been selectedto cause the scan to proceed to other trunk groups in succession; andmeans responsive to completion of the first scan without seleeting anidle path to proceed to a second scan to select a path from one of thegroups at the lowest level of preference indicated by the statuscircuit.

18. In a communication switching system, the combination as claimedinclaim 1, further including means responsive to the selection of anavailable path to record in the set of memory elements for that path thepriority level authorized for the call.

19. In a communication switching system, the combination as claimed inclaim 18, further including means to record the authorized prioritylevel in the set of memory elements for the path from which a call hasbeen originated.

20. In a communication switching system, the combination as claimed inclaim 1, further including means to select a specific individual line,and means responsive to that line being busy to preempt it if the levelof preference recorded in the set of memory elements therefor is lowerthan that authorized for the call.

